CoreSight Debug

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The CoreSightâ„¢ debug (DBG) functionality has several entry points.

  • DAP controller on the JTAG chain
  • DPC switch
  • PMC main switch

The width of the CoreSight output trace data bus can be 1, 2, 4, 8, or 16 bits wide. Higher bandwidth output can be obtained using the data packet controller (DPC) high-speed debug port (HSDP).