Cross-Trigger Interface Architecture

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The cross-trigger subsystem receives and sends trigger signals within the PS (APU and RPU) and the programmable logic (PL). There are 30+ trigger sources routed to the IN ports of the cross-trigger interface (CTI) units. The protocol between the source and the CTI can be a hardware response or a software handshake.

The cross-trigger matrix (CTM) supports four broadcast channels. Each CTI trigger input can be broadcasted on one or more channels in the CTM. Each broadcast channel can be asserted from a single trigger source, or by any number of trigger sources. All four broadcast channels are routed to all CTI units.

There are also 30+ trigger outputs from the OUT ports on the CTIs. An output trigger can be generated if one or multiple broadcast channels are asserted. The output triggers can also be programmed to assert when one or more channels are asserted. Each output trigger is routed to a destination. The protocol between the CTI trigger output and the destination can be a hardware handshake or a software acknowledgment with a write.

The cross-trigger functionality is shown in the following figure.

Figure 1. Cross-Trigger Matrix and Interface Units

CTI Units

All of the CTIs have the same programming model. All of the CTIs are listed in the CTI Summary Table with their associated register module names and links to the Versal Adaptive SoC Register Reference (AM012). The table also includes links to three groups of CTI tables. Each group includes a list of the IN and OUT ports for each CTI instance.

Some system units can only generate a trigger or receive a trigger. Some units can both send and receive triggers.

CTI Channel Protocols

When a source asserts a trigger, a status bit is set. There are two protocols for managing the status bit. The protocol for each channel is defined in the individual CTI channel tables.

  • HW handshake: the source and destination hardware set and clear the trigger status.
  • SW acknowledge: the source sets the status bit with the trigger and software must clear the status bit.
    • For IN ports, write to the source of the trigger.
    • For OUT ports, write to the CTIINTACK register.

There are separate status bits for the IN and OUT ports.