The DDR I/O banks are specifically designed to support the signals to and from the external DDR memories. For some banks, they can be connected to the PL if not needed by the associated DDR memory controller.
The I/O banks can use the XPHY to align, serialize, and deserialize a data stream. Each I/O bank has nine nibbles of six cells each for a total of 54 pins.
The input and output buffers support a wide range of single-ended and differential I/O standards along with resources to support a high level of signal quality. Each buffer has IOL resources to support low-speed SDR and DDR memory interfaces and coarse data alignment resources.
The I/O banks provide:
- 1.0V, 1.2V, 1.35V, and 1.5V bank voltage standards
- XPHY logic resources to align and serialize/deserialize high-speed data streams
- IOL resources to provide simplified lower-speed SDR and DDR memory logic support
- Internally generated VREF support shared across nibble boundaries
- Calibrated output drive support
- Calibrated internal termination
- Internal differential termination and bias offset
- Transmitter pre-emphasis and receiver equalization
- Native MIPI D-PHY interfacing
- Serialization/deserialization ratios of 1:8, 1:4, and 1:2
The I/O banks located in the left and right southern corners of the die are not accessible to the PL. In very small devices, I/O banks are not accessible to the PL.
The IOL and IOB resources for the XPIO banks are described in the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010) and with layout information in the Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013).