The integrated DDR memory controller (DDRMC) is attached to the NoC interconnect. The controller supports both the DDR4 and LPDDR4 memory interfaces. It can be configured with a 32-bit or 64-bit DRAM data interface with or without ECC. Some devices include multiple DDR memory controllers. The DDRMC has four NoC interface ports to handle multiple streams of traffic and supports quality of service (QoS) classes to ensure appropriate prioritization of the memory requests inside the controller.
Each DDRMC also includes a Xilinx memory protection unit (XMPU) to only allow authorized accesses by specific transactions with proper security and read/write attributes.
For more information on the integrated DDRMC, see the Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).