DLL Programming Example

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The example clock divider and tap settings assume the following:

  • SDx_REF_CLK is set to 200 MHz
  • SD_DLL_REF_CLK is set to 1200 MHz

Clock Divider

When the DLL is used, the reference frequency must be set to 1200 MHz. The clock divider is programmed using two fields in the SD_eMMC CLK_CTRL register.

  • [SDClkFreqDiv_L]
  • [SDClkFreqDiv_U]

TX DLL Tap Setting

The TX DLL tap settings depend on the controller mode, but are independent of the controller and the MIO path. The TX DLL tap is selected using the SD_eMMC OTAP_DLY [sel] bit field.

RX DLL Tap Setting Example

The RX DLL tap settings depend on the controller mode, the controller number, the MIO path, and board layout. The RX DLL tap is selected using the SD_eMMC ITAP_DLY [sel] bit field.

The following table shows example settings for manual tuning.

Table 1. SD/eMMC DLL Setting Example
Controller Mode Clk_Divider Frequency RX DLL Tap Setting TX DLL Tap Setting
SD/eMMC 0 SD/eMMC 1
MIO Bank 0 MIO Bank 1 MIO Bank 0 MIO Bank 1 All Options
SD 50 12 100 MHz 14h 13h 13h 14h 03h
SD DDR 24 50 MHz 14h 14h 14h 14h 03h
SD HSD 24 50 MHz 17h 17h 17h 17h 04h
eMMC DDR 24 50 MHz 14h 14h 14h 14h 05h
eMMC HSD 24 50 MHz 17h 17h 17h 17h 05h

RX Tap Programming Note

To avoid clock glitches from propagating to the external device, shut off the clock while programming the RX tap unit. Use the SD_eMMC ITAP_DLY [change_window] bit to gate the clock:

  • Turn off the clock and set [change_window] bit = 1
  • Program the RX tap value
  • Turn on the clock and set [change_window] bit = 0