DMA AXI Interface

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The DMA AXI interface is attached to the LPD source IOP switch and is clocked by the LPD_IOP_SW_CLK interconnect. It generates a 44 or 48-bit address and 64-bit wide data words. When the transaction is routed to the SMMU, a 48-bit address is used. Otherwise, only lower 44 bits are meaningful.

The DMA is controlled by a descriptor list. Packets are read from memory by the DMA and forwarded to the TX packet buffer for the MAC transmitter using the TX descriptor list. Packets are received from the RX packet buffer and written to system memory using the RX descriptor list.

Interface Clock

The DMA AXI interface is clocked by the LPD_IOP_SW_CLK switch.