DMA Channel Registers

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID: AM011
Release Date: 2023-10-05
Revision: 1.6 English

The LPD DMA registers are listed in the following table. The register base address for each channel is:

Channel 0, 0xFFA8_0000
Channel 1, 0xFFA9_0000
Channel 2, 0xFFAA_0000
Channel 3, 0xFFAB_0000
Channel 4, 0xFFAC_0000
Channel 5, 0xFFAD_0000
Channel 6, 0xFFAE_0000
Channel 7, 0xFFAF_0000

Table 1. LPD DMA Channel Register Set
Register Name	Offset Address	Access Type	Description
ERR_CTRL	`0x000`	RW	APB address decode error
CH_ISR CH_IMR CH_IER CH_IDR	`0x100` `0x104` `0x108` `0x10C`	WTC, R W W	Interrupt status, mask, enable, and disable
CH_CTRL0 CH_CTRL1 CH_CTRL2	`0x110` `0x114` `0x200`	RW	Controls
CH_FCI	`0x118`	RW	Flow control interface
CH_STATUS	`0x11C`	R	State of channel
CH_DATA_ATTR CH_DSCR_ATTR	`0x1200x124`	RW RW	Data and descriptor AXI parameters
CH_SRC_DSCR_WD0 CH_SRC_DSCR_WD1 CH_SRC_DSCR_WD2 CH_SRC_DSCR_WD3	`0x128` `0x12C` `0x130` `0x134`	RW	Source descriptor words
CH_DST_DSCR_WD0 CH_DST_DSCR_WD1 CH_DST_DSCR_WD2 CH_DST_DSCR_WD3	`0x138` `0x13C` `0x140` `0x144`	RW	Destination descriptor words
CH_WR_ONLY_WD0 CH_WR_ONLY_WD1 CH_WR_ONLY_WD2 CH_WR_ONLY_WD3	`0x148` `0x14C` `0x150` `0x154`	RW	Write only data words
CH_SRC_START_L CH_SRC_START_H	`0x158` `0x15C`	RW	Source descriptor start address
CH_DST_START_L CH_DST_START_H	`0x160` `0x164`	RW	Destination descriptor start address
CH_RATE_CTRL	`0x18C`	RW	Rate control count
CH_IRQ_SRC_ACCT	`0x1900x194`	RW RW	Source and destination interrupt account count