DMA Command FIFO

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The 2-deep command FIFO allows software to have up to two commands to the DST DMA module and up to two commands to the SRC DMA module.

Note: Only the SRC/DST_ADDR_L, SRC/DST _ADDR_U, and SCR/DST _SIZE [size, last_word] register and field values are stored in the command FIFO. All the other DMA configuration fields are read from the programming registers, which means the others are considered static for the duration of the DMA activity

For each new command, the address register must be written before the SIZE [size, last_word] register bit fields. The write to the SCR/DST _SIZE register generates an entry in the command FIFO. The FIFO-FULL status can be read via an APB register. If the FIFO is full and a write is attempted, no command is written and an interrupt bit is set to indicate the error.

As soon as there is a command loaded into the command FIFO, the DMA module starts processing. When it is completely done with the previous command, it starts processing the next command, if one is available.