DMA Features

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
Release Date
1.6 English

The DMA includes the following features:

  • Separate read channel (SRC) and write channel (DST)
  • Simple DMA, no scatter-gather
  • DST connects to 32-bit AXI to PMC IOP interconnect
  • 128-word FIFO
  • SRC DMA reads from flash memory controller when space is available in FIFO
  • DST DMA writes data when data is available in the FIFO
  • DMA start address is 4-byte aligned
  • DMA transfer length is in 4-byte words
  • DST DMA INCR burst type
  • Timeout mechanisms for SRC and DST DMA
  • Automatic DST DMA hardware management for 4 KB boundary crossing
  • Configurable AXI AxUSER bits for coherency and QoS