DRAM System Memory Controller

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English
The integrated DDR memory controller (DDRMC) supports both the DDR4 and LPDDR4 memory interfaces.
  • DDR4 memory controller (x32 and x64 with ECC)
  • HBM interface controller (x with ECC)

The DDRMC can be configured with a 32-bit or 64-bit DRAM interface with or without ECC. All devices have at least one DDR memory controller, and some devices include multiple DDR memory controllers.

The controller has four NoC interface ports to handle multiple streams of traffic and supports five quality of service (QoS) classes to ensure appropriate prioritization of the memory requests. The controller accepts burst transactions and implements command reordering to maximize the efficiency of the memory interface. Reliability features include error correction, address parity, and DQS gate tracking. Power saving features include DRAM self-refresh and automatic DRAM power down.

For more information on the integrated DDRMC, see the Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).