DSP Engine

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The DSP Engine combines high speed with small size to provide high performance and system design flexibility. The DSP Engines are integrated into the PL.

Each engine includes a dedicated 27 × 24 bit multiplier and a 58-bit accumulator. The multiplier can be dynamically bypassed, and two 58-bit inputs can feed a single-instruction multiple-data (SIMD) arithmetic unit (dual 24-bit or quad 12-bit add/subtract/accumulate), or a logic unit that can generate any one of ten different logic functions on the two operands.

New functional modes are implemented in the DSP Engine, including:

  • 18 x 18 + 58 two's complement MAC with back-to-back DSP Engines
  • Single-precision floating-point (binary32) accumulation
  • Three-element two's complement vector dot product with accumulate or post-add in INT8 mode

For more information, see the Versal ACAP DSP Engine Architecture Manual (AM004).