Data Flow Diagrams

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The TPIU connections to the DPC, MIO pins, and PL pins are shown in the following figure.

Note: At a system level, the TPIU block is shown in the Integrated Debug Block Diagram section with connections to the TPIU bridge and debug packet controller.
Figure 1. TPIU Data Flow Diagrams