Data Flow Diagrams

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The TPIU connections to the DPC, MIO pins, and PL pins are shown in the following figure.

Note: At a system level, the TPIU block is shown in the Integrated Debug Block Diagram section with connections to the TPIU bridge and debug packet controller.
Figure 1. TPIU Data Flow Diagrams