Debug Host Interfaces

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The DPC interacts with one or more of the following external debug hosts.

  • Serial, low-speed JTAG interface attached to the debug access port (DAP) controller
  • Serial, high-speed debug port (HSDP) connected to the Aurora protocol unit
  • Parallel, high-speed PCIe interface with debug protocols connected to the GTY quad transceivers
  • Parallel PL path for potential soft Aurora IP or other debug interface and protocol in the PL
Note: The JTAG interface is often used to start up the DPC and enable additional debug host interfaces.
Note: The quad GTY transceiver multiplexing options are shown in the GTY and GTYP Pipe Transceivers section of the Device I/O Connectivity chapter.

The DPC can switch between these four debug hosts as needed. The DPC transaction layer is for receiving commands packets and sending data packets. The four debug port interfaces are summarized in the following table.

Table 1. Debug Host Interface Options
Interface Description Comparison
HSDP to Aurora block Aurora hardened interface attached to a gigabit GTY transceiver. The HSDP interface consumes an entire GTY quad, but uses only one channel. Preferred choice, when available. Uses HSDP to enable high-speed operation with the capability to daisy-chain multiple Versal ACAPs for debugging multiple devices on the same board.
CPM PCIe PCIe interface access via GTY gigabit transceivers, and CPM PCIe block Another high-speed interface using PCIe throughput. Transmits DPC packets using a PCIe debug protocol.
PL Instantiated Aurora block PL fabric interface access via AXI4-Stream into PL to enable soft Aurora Can be selected when no other choice is available. Can also be considered an HSDP if full protocol is implemented. DPC access is available after the PL design has been loaded.
JTAG interface JTAG IEEE 1149.1 standard interface with debug instruction Bandwidth is limited by the JTAG performance.