Debug Resets

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
Release Date
1.6 English

The CoreSightâ„¢ debug functionality is spread across all the power domains. The PLM is aware of the states of the power domains and is responsible for the appropriate distribution of the debug reset.

The debug reset is passed to all CoreSight components within the PMC, LPD, FPD, and CPM through PMC reset register bits. The debug port controller (DPC) is reset by a register in the TAP controller, which is accessed through the PMC interconnect.

At the device level, this reset also applies to the high-speed debug port (HSDP) through the RST_DBG_LPD [RST_HSDP] bit. If the soft Aurora is implemented in the PL, a PMC GPO bit can be used to reset the logic. The PL debug components are separated from mission IPs and are placed on a separate reset. The DDR memory controller, NoC interconnect, and AI Engine resets are controlled through four NPI controls, which allows the partitioning of the resources into groups and associates each group with a specific reset category.

The debug logic includes the DPC in the PMC and the CoreSight logic that extends into the PMC, PS, PL, and other parts of the device. The debug resets are summarized in the following table.

Table 1. Debug Resets
Description Reset Name Power Domain Register Bit Control Notes
CRP RST_DBG register
All CoreSight components inside of the PMC and PS CORESIGHT_RESET PMC, LPD, and FPD [RESET]

Includes logic affected by the: CRL CRL.RST_DBG_LPD [1:0] and CRF CRF.RST_DBG_FPD [0] register bits.
Does not reset the DPC in the PMC.

Debug port controller DPC_RESET PMC [DPC] PMC DPC logic.
CRL RST_DBG_LPD register
LPD CoreSight and all FPD debug components PS_DEBUG_RESET LPD and FPD [RESET]  

LPD portions of Aurora and the DPC DMA controllers (not the RAM).

RPU debug logic




Includes RPU debug logic, breakpoint, and watchpoint.