TSGEN is the debug timestamp generator. The CTRL register controls the counter operation by enabling, disabling, or halting the counter. Normally, it is 400 MHz after boot, but the frequency can be changed using the CRL DBG_TSTMP_CTRL register.
TSGEN is the debug timestamp generator. The CTRL register controls the counter operation by enabling, disabling, or halting the counter. Normally, it is 400 MHz after boot, but the frequency can be changed using the CRL DBG_TSTMP_CTRL register.