Descriptions

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

Descriptor Access Done Interrupt

Each time a descriptor entry is done, the PS_DMA CH_ISR [SRC_DSCR_DONE, 1] or [DST_DSCR_DONE, 2] interrupt bit is asserted for read and write operations, respectively.

Accounting Done Overflow Interrupts

The accounting overflow occurs when the number of descriptors processed exceeds the programmed count.

When descriptor count is enabled, each descriptor done event increments a descriptor done counter. There are separate accounting counter registers for SRC and DST transactions; PS_DMA CH_ISR [IRQ_SRC_ACCT] and [IRQ_DST_ACCT] bits.

An interrupt accounting counter overflow is indicated as a SRC or DST interrupt; PS_DMA CH_ISR [IRQ_SRC_ACCT_ERR, 4] and [IRQ_DST_ACCT_ERR, 5]. This is a non-fatal error as it does not affect the channel functionality.

Byte Transfer Overflow Interrupt

A transfer overflow occurs when the number of bytes transferred is more than the bytes requested.

The number of bytes to transfer is programmed in the PS_DMA CH_SRC_DSCR_WD2 and CH_DST_DSCR_WD2 [SIZE] register fields. This value is compared with an internal counter. The internal counter increments by 1 for each byte that is transferred on the interconnect. The counter is updated when the channel receives the BREP signal to show the AXI transaction is done.

Note: The internal counter continues to increment during an error.

A transfer overflow generates the PS_DMA CH_ISR [BYTE_CNT_OVRFL, 3] interrupt bit. This is a non-fatal error and does not affect the functionality of the DMA channel.

AXI Descriptor Read Errors

If an error occurs during an AXI descriptor table read transaction, a descriptor read error interrupt is generated. There are two interrupt bits; one when fetching source descriptors PS_DMA CH_ISR [AXI_RD_SRC_DSCR, 6] and one when fetching destination descriptors [AXI_RD_DST_DSCR, 7].

AXI Data Access Errors

If an error occurs during an AXI data read/write transaction, the DMA channel performs an error recovery sequence and recovers all occupied entries in the common buffer. After completing the error recovery sequence, it generates the PS_DMA CH_ISR [AXI_RD_DATA, 8] or [AXI_WR_DATA, 9] error interrupt and disables the channel.

DMA Done Interrupt

When the DMA data transfer is completed (with or without error), the controller asserts the PS_DMA CH_ISR [DMA_DONE] interrupt.

DMA Pause Interrupt

The DMA data transfer can be paused using the CH_SRC_DSCR_WD3 [CMD] bit. When this occurs, it can be seen in the CH_STATUS [STATE] and, optionally, generate an interrupt that is posted to the PS_DMA CH_ISR [DMA_PAUSE] bit.

RAM Parity Errors

The controller includes three RAM memories that are protected by parity error logic. The parity error causes bits to be set in the PS_DMA CH_ISR register:

  • Common data buffer stores data [WRBUG_PERR, 12]
  • Internal RAM indexes the slots available in the common buffer [FREE_LIST_PERR, 13]
  • Internal RAM used to manage link lists [LINK_LIST_PERR, 14]

Software Programming Errors

Software must ensure the DMA is programmed properly. The controller hardware cannot recover from a programming error. The DMA channel behavior is unpredictable.