Device Overview

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The Versal® ACAP includes extensive functionality for high-end applications that need scalable processing power, integrated functional units, and a large amount of scalable programmable logic that can be dynamically configured and reconfigured during normal operation.

The device is partitioned into the following areas:

  • Processing system (PS) with multicore application and multicore real-time processing units
  • Platform management controller (PMC) for boot, configuration, monitoring, and power management
  • PS manager (PSM) for PS power management
  • On-chip memory (OCM) and optional accelerator RAM (XRAM)
  • DDR memory controllers with ECC
  • High-bandwidth memory (HBM) option
  • Programmable logic (PL) with fabric, logic units, memory arrays, and DSP options
  • Device-wide network on chip (NoC) interconnect
  • Integrated hardware and I/O peripheral options
  • Standard LVCMOS HDIO
  • Gigabit transceiver options

The architecture includes a rich set of integrated hardware components and many user-programmable design options for system-level solutions. Each device incorporates PL,PS, PMC, and various integrated hardware subsystems and peripherals that are configured with a coherent flow. The PL and PS sections of the device each have many components that can be selectively used as needed and, if included, they are configured and initialized to accommodate different functional and power requirements demanded by the platform solution.

The PL supports AXI SmartConnect core functionality that can be instantiated using a library of LogiCORE™ IPs. The AXI SmartConnect core can be independent within the PL or extended and attached to the PS through several AXI interfaces with and without coherency with the APU system cache.

Additionally, the system is monitored during its runtime to detect errors and provide the necessary means to address the errors as a part of the security, reliability, and safety requirements. The configuration, bring-up, and general platform management tasks include reset, clocking, power management, and system monitoring. This is achieved by the PMC that exists in every device. The PMC also provides a unified interface for the cohesive debug and trace capture on the entire device including the PS, PL, and other components on the device.

All devices are based on the NoC interconnect to link processors and DMA units to system memory, other processors, and other resources within the device and to external devices with the various implementations of a coherent module with PCIe® (CPM) (a device option).

Each device has one or more DDR memory controllers. Some devices include an interface for an in-package HBM.

There are several types of I/O banks spread throughout the device to connect to external devices, including the PMC, PS, and the PL. The I/O banks include PSIO, HDIO, and the GT transceivers.

The size and composition of the PL, the number of memory controllers, the amount of I/O, and the integrated hardware blocks varies by device as defined in the Versal Architecture and Product Data Sheet: Overview (DS950).

There are several power domains with their own package power pins that are color-coded in the following section:

All blocks and subsystems are controlled and monitored with hundreds of register modules. Each module includes twenty to thousands of individual registers. These are documented in several register reference manuals. Most functional units include one register module. Some functional units have multiple register modules. Some register modules are associated with multiple functional units that include the system-level control registers (SLCR) and the clock and reset registers (e.g., CRL). The register modules for the PS and PMC units are accessed by software using single 32-bit read and write transactions to the APB programming interfaces. The register sets for the DDR memory controller, NoC, AI Engine, and other integrated hardware are accessed via the NPI host interface. This interface supports 32-bit burst reads and writes. Access to NPI register modules is controlled by XPPU protection units. The software programming interfaces to read and write registers and program the device are described in Register Programming Interfaces section.

The device documents are listed in the Documentation chapter.