ECC Operations

If errors occur due to a fault injection or other reasons, an interrupt is generated. The OCM. APB_MISC_ISR register provides the interrupt status and the cause of the error. This is a sticky register that holds the value of the interrupt until cleared by a value of 1. Read bits 6 and 7 of the status register for information on whether the error is correctable or uncorrectable.

Read Correctable Error Registers

1. Retrieve the address of the first occurrence of an access with a corrected error. Read the 18-bit [ADDR] bit field in the CE_FFA register.
2. Retrieve ECC syndrome bits of corrected error. Read CE_FFE [SYNDROME] bit field.
3. Retrieve corrected data. Read the four data words using the ocm_csr.OCM_CE_FFD0, 1, 2, and:3registers.

Read Uncorrectable Error Registers

1. Retrieve the address of the first occurrence of an access with an uncorrected error. Read the 18-bit [ADDR] bit field in the UE_FFA register.
2. Retrieve ECC syndrome bits of uncorrected error. Read UE_FFE [SYNDROME] bit field.
3. Retrieve uncorrected data. Read the four data words using the UE_FFD0 , 1, 2 and 3 registers.

Inject Error

Errors can be injected into a RAM array.

1. Enable error response by setting the third bit of the ERR_CTRL register.
2. Enable ECC by setting the zeroth bit of the ECC_CTRL register.
3. To only detect single bit errors, set the first bit of the ECC_CTRL register. By default this bit is zero and it indicates that single-bit errors are corrected.
4. To inject an error on every write after fault injection count cycle, set the second bit of the ECC_CTRL register. If a zero is programmed for the same bit in the register, then only a single fault is injected.
5. The fault injection count must be programmed by setting the required value in the first 24 bits of the FI_CNTR register.
6. A fault can be injected into the syndrome bits using the FI_SY register. Faults in the data words can be injected using the FI_D0 , 1, 2, and 3 registers.
7. Interrupts can be enabled for different errors by setting the required bits of the APB_MISC_IER register.
8. Unwanted interrupts can be disabled by setting the required bits of the APB_MISC_IDR register.
9. Reading the APB_MISC_IMR register gives information regarding the type of interrupts that are masked out. This is a read-only register and reflects the settings done on the IER and IDR registers.