EMIO Signals

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
Release Date
1.6 English

For each GPIO channel, there are three signals routed to the PL: input, output, and output enable.

The register interface for the EMIO banks is the same as for the MIO banks. However, the EMIO interface is simply wires between the PS and the PL, so there are a few differences:

  • The inputs are wires from the PL and are unrelated to the output values or the OEN register. They can be read from the DATA_RO register when DIRM is set to 0, making it an input.
  • The output wires are not 3-state capable, so they are unaffected by OEN. The value to be output is programmed using the DATA, MASK_DATA_LSW, and MASK_DATA_MSW registers. DIRM must be set to 1, making it an output.
  • The output enable wires are simply outputs from the PS. These are controlled by the DIRM/OEN registers as follows: EMIOGPIOTN[x] = DIRM[x] & OEN[x].

The EMIO I/Os are not connected to the MIO I/Os in any way. The EMIO inputs cannot be connected to the MIO outputs and the MIO inputs cannot be connected to the EMIO outputs. Each bank is independent and can only be used as software observable/controllable signals.

Table 1. GPIO PL EMIO Signals
EMIO Port Signals
GPIO Bank Signal Name I/O
PMC Bank 3 [0:31] Input_x I
Output_x O
Output_En_x O
PMC Bank 4 [0:31] Input_x I
Output_x O
Output_En_x O
LPD Bank 3 [0:31] Input_x I
Output_x O
Output_En_x O