There are many RAM memory arrays embedded in the Versal device. Most are protected by parity or ECC to support safety applications. The embedded memories are summarized with additional documentation references in the Memory section of the TRM.
The on-chip memory (OCM) is accessible from the LPD OCM interconnect switch. The OCM is described in the On-Chip Memory section.
PMC RAM Memory
The PMC includes the PPU and PMC memories:
- 256 KB PPU processor RAM for instruction and data
- 128 KB PMC system RAM for data structures
RPU Tightly-coupled Memory
Each RPU core includes 128 KB of tightly-coupled memory (TCM) in three banks per core. Each pair of cores can be configured in two groups for high-performance dual processor mode, and grouped together for high-safety, lock-step mode. All of these memories are ECC protected.
- See the Tightly-coupled Memories section in the Versal ACAP RPU chapter.
The PL includes block RAM and UltraRAM memory cores scattered throughout the array, which includes ECC bits on 64 byte data segments. The block RAM and UltraRAM are described in the Versal ACAP Memory Resources Architecture Manual (AM007).
Buffers, FIFOs, and Caches
The last group of RAMs are scattered in various blocks for buffers, FIFOs, and caches.