There are three embedded microprocessors.
- ROM code unit (RCU) executes the BootROM code from ROM, see the ROM Code Unit chapter.
- PPU processor executes the platform loader and manage (PLM) firmware running in the platform processing unit (PPU) with access to its local PPU RAM and the PMC RAM.
- PSM processor executes the PSM firmware from RAM, see the Processing System Manager chapter.
The functionality of the BootROM code is described in the Platform Boot, Control, and Status section.
The functionality of the PLM and PSM firmware is described in the Versal Adaptive SoC System Software Developers Guide (UG1304). The MicroBlaze processor is described in the MicroBlaze Processor Reference Guide (UG984).
RCU BootROM Code
The deeply embedded RCU is the first processor to start up after a system reset (SRST) or power-on reset (POR). The RCU executes its BootROM code to initialize the hardware and validate the boot device; this includes processing the boot header that is accessed from the boot device. The RCU downloads the PLM firmware into the PPU RAM. The hardware is ready, the RCU releases the reset on the PPU processor to begin execution of the PLM firmware.
The RCU BootROM code and PLM firmware work together to provide platform attestation services. The platform attestation services make use of platform configuration registers (PCRs), manufacturing endorsement keys, and device identifier composition engine (DICE) support.
For more information, see the Versal Adaptive SoC Security Manual (UG1508). Security libraries are documented in the Versal Security Libraries User Guide (UG1540). Security documents require an active NDA to download from the Design Security Lounge.
PLM Firmware Code
The PLM firmware runs on the MicroBlaze-based platform processing unit (PPU). The PLM firmware is generated by the AMD Vivado™ and AMD Vitis™ tools and configures the system for device boot. The PLM firmware includes code to support a single image or a series of image downloads. After system boot, the PLM goes on to manage system resources.
The PLM reads the programmable device image (PDI) from the boot source, and initializes and configures the system components for the APU and RPU subsystems. The PLM configuration normally includes NoC initialization, DDR memory controller initialization, programmable logic configuration, and loading real-time and application software in the processing system. The operations and responsibilities of the PLM are defined by the SoC application. When the processing system takes control of the SoC, the PLM monitors system activity and responses to system requests from the real-time and application processing units, RPU, APU, and the programmable logic.
PSM Firmware Code
The PSM executes firmware downloaded by the PLM to control the power management features for the processing system and other subsystems. The technical reference manual provides programming models for the power control features in the PMC and PS. This includes power islands, memory chip enables, isolation, and APU sleep/wake events. The PSM is physically located in the low-power domain (LPD), and not the PMC power domain.
The embedded processing system manager processor is located in the PS LPD.