There are three embedded MicroBlaze processors.
- ROM code unit (RCU) executes the BootROM code from read-only memory (ROM)
- PPU processor executes the PLM firmware from RAM, see the Platform Processing Unit chapter
- PSM processor executes the PSM firmware from RAM, see the Processing System Manager chapter
The functionality of the BootROM code is described in the Platform Boot, Control, and Status section. The functionality of the PLM and PSM firmware is described in the Versal ACAP System Software Developers Guide (UG1304). The MicroBlaze processor is described in the MicroBlaze Processor Reference Guide (UG984).
RCU BootROM Code
The deeply embedded RCU is the first processor to start up after a power-on reset (POR). The RCU executes its BootROM code to initialize the system and validate the boot device. The RCU processes the boot header provided by the boot device. The RCU downloads the platform loader and manager (PLM) firmware into the PPU RAM and releases the reset on the PPU processor.
PLM Firmware Code
The PLM firmware runs on the MicroBlaze-based platform processing unit (PPU). The PLM firmware is generated by the Vivado® and Vitis™ tools and configures the system for device boot. The PLM firmware includes code to support a single download or a series of downloads. After system boot, the PLM goes on to manage system resources.
The PLM reads the programmable device image (PDI) from the boot source and configures the system components for real-time and application program booting. The PLM configuration normally includes NoC initialization, DDR memory controller initialization, programmable logic configuration, and loading real-time and application software in the processing system (PS). The operations and responsibilities of the PLM are defined by the SoC application. When the PS takes control of the SoC, the PLM monitors system activity and responses to system requests from the real-time and application processing units, RPU and APU.
PSM Firmware Code
The embedded processing system manager (PSM) processor executes firmware downloaded by the PLM to control the power management features for the PS. The TRM provides programming models for the power control features in the PMC and PS. This includes power islands, memory chip enables, isolation, and APU sleep/wake events. The PSM is physically located in the low-power domain (LPD), and not the PMC power domain.