Enabled RX Buffer

Versal Adaptive SoC Technical Reference Manual (AM011)
Document ID
AM011
Release Date
2023-10-05
Revision
1.6 English

In this case, the [RXFP] field (in the RxBuff_Watermark watermark register) along with the Acceptance Filter (Control) register determines whether received messages are stored in RX buffer 0 or in RX buffer 1. In this case, note that the [RXFP] field should be less than 31d.

  1. The incoming identifier is masked with the bits in the Acceptance Filter Mask register.
  2. The AF_ID_Reg_n acceptance filter ID register is also masked with the bits in the associated AF_Mask_Reg_n register.
  3. Both resulting values are compared.
  4. If both these values are equal and the matched filter index is less than equal to the [RXFP] field, the message is stored in RX buffer 0.
  5. Otherwise, if both these values are equal and the matched filter index is greater than the [RXFP] field, the message is stored in RX buffer 1.
Note: The ID match process is a sequential process. It starts from the lowest enabled filter and stops at first match. Consequently, if an incoming message fulfills condition 4 but RX buffer 0 is full, the message is dropped (irrespective of RX buffer 1 status) and RX buffer 0 overflow is indicated.

Similarly, if an incoming message fulfills condition 5 and RX buffer 1 is full, the message is dropped (irrespective of the RX buffer 0 status) and RX buffer 1 overflow is indicated.

Note: If all of the [UAF] bits in the AF_Control are set to 0, the received messages are not stored in any RX buffer.
Note: Filter pair registers are stored in the RAM. The host must ensure that each used filter pair is properly initialized. Asserting a software reset or system reset does not clear these register contents.
Note: The host must initialize/update/change the filter pair only when the corresponding UAF is 0.
Important: Ensure proper programming of the [IDE] bit in the TxBuff_ID_Msg_n register for standard and extended frames in an AF_Mask_Reg_n acceptance filter mask and AF_ID_Reg_n acceptance filter ID register. If the [IDE] bit in the mask register is set to 0, it is considered to be a standard frame ID check only. Consequently, if the standard ID bits of the incoming message match with the respective bits of the filter ID (after applying the mask register bits), the message is stored.