Error Interrupt

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The error interrupt is asserted when an error occurs in the reception of data by the UART. The interrupt can be caused by a number of different error conditions:

  • Framing
  • Parity
  • Break
  • Overrun

The cause of the interrupt can be determined by reading the Raw Interrupt Status register, INTR_RIS or the Masked Interrupt Status register, INTR_MIS . It can be cleared by writing to the relevant bits of the Interrupt Clear register, INTR_CLR (bits 7 to 10 are the error clear bits).