Errors

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The following table lists the possible errors that can be encountered by the protection unit and how they are handled.

Table 1. Error Handling in XPPU
Error 1 Actions
SMID list parity error The SMID_nn register associated with the parity error is disabled and cannot enable a match, that is, MATCH [nn] is forced to 0. The SMID_PARITY bit of the ISR register is set and an interrupt can optionally be signaled.
SMID list read only error A SMID read-only error occurs when any of the matched SMID_nn register enabled by the [permission] field of the selected aperture, its [SMID_R] bit is set, and the transaction is a write. When multiple SMIDs are both matched and enabled and one or more have [SMID_R] bits set, a SMID read-only error is still flagged and the [SMID_RO] bit of the ISR register is set.
SMID list miss error When an aperture is activated, but all the [permission] bits are 0, an miss error occurs. The [SMID_MISS] bit of the ISR register is set.
Aperture permission list parity error The transaction is disallowed and [APER_PARITY] bit of the ISR register is set. An interrupt can optionally be signaled.
Transaction TrustZone error 2 When a non-secure transaction attempts to access a secure slave, a transaction TrustZone error occurs. This error is flagged only when there is no miss error and no aperture parity error. The transaction fails and an interrupt can optionally be signaled.
Transaction permission error 2 When a transaction is not allowed, a transaction permission error occurs. An access to an address that is not covered by the XPPU causes this type of error. This error is flagged only when there is no SMID_MISS error and no aperture parity error. This error is not flagged when there is a SMID_MISS error or an aperture parity error. The transaction fails. An interrupt can optionally be signaled.
  1. Access to an address not covered by the aperture permission registers goes through the XPPU intact.
  2. The first transaction address, SMID, and read/write mode are captured for debugging. When there are simultaneous read/write errors, only the write error is recorded. Only the first error is recorded. To record further errors, the ISR (interrupt status register) must be cleared first.