Events and Performance Monitor Unit

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The processor includes logic to detect various events that can occur, for example, a cache miss. These events provide useful information about the behavior of the processor to use when debugging or profiling code.

The events are made visible on an output event bus and can be counted using registers in the performance monitoring unit (PMU). The registers are located in the DBG_A720_PMU and DBG_A721_PMU register modules for APU0 and APU1.