External Memories

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

External memory is controlled by on-chip memory controllers:

  • DDR memory controller (DDR MC)
  • Flash memory controllers (QSPI, OSPI, SD_eMMC)
  • High-bandwidth memory (HBM) interfaces

DDR Memory Controller

The integrated DDR memory controller (DDRMC) supports both the DDR4 and LPDDR4 memory interfaces. It can be configured with a 32-bit or 64-bit DRAM interface with or without ECC. All devices have at least one DDR memory controller, and some devices include multiple DDR memory controllers.

The controller has four NoC interface ports to handle multiple streams of traffic and supports five quality of service (QoS) classes to ensure appropriate prioritization of the memory requests. The controller accepts burst transactions and implements command reordering to maximize the efficiency of the memory interface. Reliability features include error correction, address parity, and DQS gate tracking. Power saving features include DRAM self-refresh and automatic DRAM power down.

For more information on the integrated DDRMC, see the Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).

Flash Memory Controllers (in PMC)

The flash memory controllers are introduced in PMC I/O Signals with details in Flash Memory Controllers.

  • Quad SPI controller
  • Octal SPI controller
  • Two SD/eMMC controllers

High-Bandwidth Memory Interfaces

The HBM interfaces are briefly described in the High-Bandwidth Memory Interface section. The physical layout of the HBM interface is described in the Si Interposer Design for High-bandwidth Memory section.