FPD Functional Units

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The following table lists the FPD functional units.

Table 1. FPD Functional Units
Unit Description Links
Compute Resources
APU processor engine Two-core or four-core Arm® Cortex-A72, v8-architecture See APU Processor Implementations for more processor-related functional units and Application Processing Unit for descriptions
FPD_SWDT System watchdog timer (SWDT) for software integrity monitoring System Watchdog Timers
AXI interconnect AXI interconnect switches, NIC-400 AXI Interconnect Switches
Cache coherent interconnect (CCI) Connects APU processors and SMMU traffic to shared 1 MB L2 cache Cache Coherent Interconnect
SMMU System memory management unit with translation control unit and several individual translation buffer units (TBU) to translate virtual address into physical address System Memory Management Unit
Non-coherent interconnect I/O peripheral switch, and APB programming interface
FPD_XMPU Memory protection unit for register and system modules Xilinx Memory Protection Unit
Test and Debug Resources
DBG registers CoreSight CoreSight Architecture