FPD Interconnect Diagram

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The FPD includes the Cortex-A72 application processor MPCore (APU) with an L2 cache attached to a Cache Coherent Interconnect (CCI). The transactions originating outside of the APU can be routed to the system memory management unit (SMMU) to allow them access to APU shared memory and the APU L2-cache.

The CCI includes ACE ports to provide full APU L2-cache coherency with the PL. The two ACE ports can snoop the caches of the two attached processors.

Other transaction hosts connect to the ACE-Lite ingress ports (iPorts) ports on the CCI to optionally provide I/O coherency of their transactions with the APU L2 cache (including the RPU but excluding the LPD DMA unit).

See Cache Coherent Interconnect chapter for more information.

The FPD interconnect is shown in the following figure.

Figure 1. PS FPD Interconnect Diagram