FPD Reference Clocks

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

FPD Clock Divider Control Registers

The FPD clock dividers are controlled by registers in the CRF register set. The FPD reference clock control registers are listed in the following table.

Table 1. FPD Reference Clock Control Registers
Description Clocks Control Register
Output Name Divider Input Options
APU: CPUs, L2-cache, debug logic, controls

CoreSight components: ELA500, funnel, ETF, CTI

APU_REF_CLK APLL_CLK RPLL_TO_XPD_CLK PPLL_TO_XPD_CLK NPLL_TO_XPD_CLK APU_CTRL
Trace port for CoreSight debug data flow DBG_TRACE_CLK DBG_TRACE_CTRL
FPD CoreSight debug components DBG_FPD_CLK DBG_FPD_CTRL
FPD APB programming interfaces FPD_LSBUS_CLK FPD_LSBUS_CTRL
FPD AXI main switch FPD_TOPSW_CLK FPD_TOPSW_CTRL