Fail Counter

Versal ACAP Technical Reference Manual (AM011)

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1.5 English

The 3-bit fail counter (FC) keeps track of the accuracy of the interactions between the software and the watchdog timer. The fail counter tracks good and bad watchdog events. For every good event, the fail counter decrements by 1 (unless it is at 0). For every bad event, the fail counter increments by 1 (unless it is at 7).

When the FC is 7 and another bad event occurs in the first window, the timer continues counting through the first window but skips the second window. If the SST Second Sequence Timer (SST) window is enabled, the pending reset event occurs followed by the eventual system reset.

When the FC is 7 and another bad event happens in the second window, the timer immediately goes to either the SST window (if enabled) or directly to asserting the system reset.

The watchdog timer can only be disabled when the fail counter is 0.

The FC reset value is 5 but can be changed by software before enabling the watchdog timer.

  • FC in basic mode (optional)
    • The fail counter is enable by the Funct_Ctrl [FCE] bit
  • FC in Q&A mode
    • Always enabled

The last bad event type is recorded in the Enable_and_Status [LBE] bit field. The event types are listed in the Features and Options table and in the register manual.