Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
Release Date
1.6 English

When enabled, the MAC receiver filter determines which frames should be written to the RXFIFO.

Filtering includes:

  • State of the I/O matching signals
  • Register programming:
    • Specific address
    • Specific type
    • Hash
  • Destination address and type field of the field

If the Network_Config [en_half_duplex_rx, 25] is set = 0, a frame is not placed in the RXFIFO if transmitting in half-duplex mode at the time a destination address is received.

Ethernet frames are transmitted a byte at a time, least significant bit first. The first six bytes (48 bits) of an Ethernet frame make up the destination address. The first bit of the destination address (least significant bit of the first byte) defines the casting:

  • 0: Unicast address
  • 1: Multicast address

An address of all 1's is a special case of the multicast, broadcast address.

Address Filtering using Four Specific Addresses

The MAC receiver recognizes up to four specific addresses. Each specific address requires two registers: Spec_Addr1_U (two bytes) and Spec_Addr1_L (four bytes). The address stored can be specific, group, local, or universal.

When address filtering is enabled, the RX frame destination address is compared against up to four specific addresses stored in registers. If a receive frame address matches an active specific address, the frame is written to the RX packet buffer.

Address filtering is activated when the spec_add1_top register is written; therefore write, the spec_add1_bottom register first. Filtering is deactivated by writing to the Spec_Addr1_L register or by the GEM_RESET.

Specific Type ID Filtering

Frame-specific type IDs are used by software to identify a particular stream of traffic. They can be filtered using the specific ID match registers. Four ID registers are available. An ID match register (e.g., Spec_ID1_Match ) is enabled writing a 1 to the [enable_copy, 31] bit. When a frame is received, the enabled ID matching results (up to 4) are OR'd together.

The contents of each specific type ID match register (e.g., Spec_ID1_Match ) is compared against the length/specific type ID of the frame being received (for example, bytes 13 and 14 in non-VLAN and non-SNAP encapsulated frames) and written into the RxFIFO if a match is found. The encoded spec ID match bits (word 1, bit [22] and bit [23]) in the receive buffer descriptor status are set to indicate which specific type ID match register generated the match, if the receive checksum offload is disabled. The reset state of the specific type ID match registers is zero and is disabled.

Filtering Example

This example illustrates the use of the specific address and ID match registers for a MAC address of 21:43:65:87:A9:CB. The sequence in the following table shows the beginning of an RX frame. The byte order of transmission starts with the preamble, shown at the top of the table.

For a successful match to specific address 1 register, write the destination address.

Note: In this example, the address mask bits are all disabled (reset value).

For a successful match to the specific type ID1 match register, write the ID and enable the register:

Table 1. GEM Address and Type ID Filtering Example
Byte Type Example Value Description
Preamble 55  
SFD D5 Start frame delimiter
DA (octet 0, LSB) 21 Destination address
DA (octet 1) 43
DA (octet 2) 65
DA (octet 3) 87
DA (octet 4) A9
DA (octet 5, MSB) CB
SA (octet 0, LSB) xx Address of transmitting device
SA (octet 1) xx
SA (octet 2) xx
SA (octet 3) xx
SA (octet 4) xx
SA (octet 5, MSB) xx
Specific Type ID (MSB) 43 Type ID match 1
Specific Type ID (LSB) 21