Flash Memory Controller Clock Frequency Requirements

Versal ACAP Technical Reference Manual (AM011)
Document ID
AM011
Release Date
2022-12-16
Revision
1.5 English

The flash memory controller clock frequency requirements are listed in the following table.

Table 1. Flash Memory Controller Clock Frequency Requirements
Controller and Mode Description
Quad-SPI Controller, see the QSPI Clocks section
  Dual parallel, non-manual mode PMC_IRO_CLK > 3/7 * QSPI_REF_CLK
Single quad, non-manual mode PMC_IRO_CLK > 3/15 * QSPI_REF_CLK
Dual quad, non-manual mode PMC_IRO_CLK > 3/31 * QSPI_REF_CLK
Manual mode, CPOL=1 and CPHA=1

QSPI_REF_CLK ≥ PMC_LSBUS_CLK
All modes with QSPIx_CLK frequency > 37.5 MHz

QSPI_REF_CLK > 2 * QSPIx_CLK

Octal-SPI Controller, see the OSPI Clocks section
  DLL mode

OSPI_CLK = OSPI_REF_CLK
Non-DLL mode

OSPI_CLK ≤ OSPI_REF_CLK / 4
SD_eMMC Controller, see the SD Clocks section
  DLL mode

SD_DLL_REF_CLK ≥ 6 * SDx_REF_CLK
Note: This requires setting the DLL divider to 6 (reset value) or greater.

Source these clocks from the same PLL:
SD_DLL_REF_CLK, SD0_REF_CLK and SD1_REF_CLK