Flow-Control Programming Model

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

After each DMA transaction is done, the DMA channel clears both the channel enable PS_DMA.CH_CTRL2 [EN] and FCI enable PS_DMA.FCI_EN [EN] register bits. The software must re-enable the FCI interface for each DMA transaction. If the FCI interface is not enabled, PS_DMA.FCI_EN [EN] = 0, the DMA channel flushes all incoming credits.

Credits are only valid when the FCI interface is enabled; PS_DMA.FCI_EN [EN] = 1.

  • Setup channel mode: simple and scatter-gather (SG) mode.
  • PS_DMA.CH_DSCR_ATTR and PS_DMA.CH_DATA_ATTR registers.
  • Setup DMA mode:
    • Simple mode, program the DSCR registers.
    • SG mode, program the descriptor tables in memory and program the DSCR start address register.
  • Set the FCI control parameters, PS_DMA.CH_FCI [EN, SIDE].
  • Set the enable bit, CH2_CTRL [EN]. This triggers the DMA channel to operate.

The DMA channel provides transaction acknowledgment for all valid credits received after the PS_DMA.CH_FCI [EN] enable bit is set. The DMA channel clears the enable after the controller is done with the DMA transaction. The software must enable FCI along with the channel enable for subsequent DMA transfers.

Suggested Use Model

The suggested use-model for applications is:

  • SRC and DST payload addresses are aligned to programmed AXI burst length and an over fetch is enabled.
  • Software provides the transfer size details to the flow control slave.

Implementation Notes

  • If the suggested use-model requirements are satisfied, attaching FCI to SRC/DST is not required.
  • When FCI is enabled, both the AXI read and write command use the same burst length SRC AXI length (ARLEN).
  • When the SRC and DST descriptor payloads are not aligned to the bus width, the number of read and write transactions could be different.
  • The size of the first and last transaction can be different based on the alignment of the read and write payload.
  • One credit means one AXI read or write transaction. The size of the transaction can vary based on the 4k boundary crossing and over fetch disable. The DMA channel never generates a transaction larger than the programmed ARLEN.
  • Read/write transactions can be controlled using more than one mechanism. A channel might not generate a transaction, even if it has credits, due to other channel control parameters.
    • Rate control counter.
    • Outstanding transaction count.