In PIO mode, the software can access the SD data port register through the AXI interface. This is the PIO method in which the host software driver transfers data using the buffer data port register. Only single transfers are allowed (no burst support). Also, only one outstanding read/write transaction is allowed.
PIO SDMA Controller
In SDMA mode, the controller interacts with the registers set and starts the DMA engine for commands with a data transfer. The controller maintains the block transfer counts for PIO operation.
The programming model is explained in Register-driven DMA Mode.
Descriptor ADMA Mode
ADMA includes a descriptor-based architecture with scatter-gather capabilities. Software creates descriptor tables in system memory that are processed in the ADMA mode.
The programming model is explained in Descriptor-driven DMA Mode.
The DMA controller supports both SDMA and ADMA modes. The DMA controller uses its AXI interface to transfer data between the block buffer and the system memory. The controller also uses this interface to access descriptor tables in system memory. The DMA controller also implements a host transaction generator to control the host master interface.
The DMA memory transactions can be routed to the FPD memory coherent interconnect for cache coherency with the system cache or be routed to a non-coherent path including a NoC port to access system memory or AXI routing to the OCM.