The high-level block diagram includes several major functional units.
TXFIFO and RXFIFO
The controller has a 64-word TXFIFO for sending content to the I/O interface and a 64-word RXFIFO for receiving data from the I/O interface. Use the QSPI.TXD register data port to write data to the TXFIFO and the RXD register data port to read data from the RXFIFO.
Software writes 20-bit command words to the command FIFO data register to configure and initiate transactions on the I/O interface. The command generator initiates transactions that are driven by the command fields. The controller transmits data written to the TXFIFO and receives data read from the RXFIFO.
- Cmd_FIFO_Data (aka GQSPI_GEN_FIFO)
The controller can repeatedly read the status of a flash device looking for a specific pattern. This can be used to monitor the status of a flash device operation or other purpose.
The DMA controller is used to move large blocks of data from the flash device to system memory. This is a master, write-only DMA controller on the AXI bus interface. It can only be used to read data from the flash device and write the data to system memory.
The controller has two system interfaces and a single I/O interface.
32-bit APB programming interface
- Memory mapped, programming registers
- Control, status, and interrupt registers
- FIFO data ports
AXI master interface for DMA controller memory writes
- 44-bit physical address with 32-word data bursts
- AxCACHE defines coherency and buffer ability of the transaction
Flash memory I/O interface
- 4 and 8-bit data I/O (one or two devices)
- QSPIx_CS_b chip select
- QSPIx_CLK device clock
- QSPI_LPBK_CLK loopback clock