GPIO Register Descriptions

Data Read and Write

• DATA_RO, read-only:

  For MIOs, this register always returns the state of the GPIO MIO pin. If the GPIO is configured as an output, this normally reflects the value being driven on the output regardless of the DIRM_x setting.

  Note: If the MIO is not configured for this pin as a GPIO, the DATA_RO returns unpredictable results.
• DATA, read-write:

  This register controls the value to be output when the GPIO signal is configured as an output. All 32 bits of this register are written at one time. Reading from this register returns the previous value written to either DATA or MASK_DATA_{LSW,MSW}, and does not return the current value on the device pin.

• MASK_DATA_LSW:

  This register enables more selective changes to the desired output value. Any combination of up to 16 bits can be written. Those bits that are not written are unchanged and hold their previous value. Reading from this register returns the previous value written to either DATA or MASK_DATA_{LSW,MSW}; it does not return the current value on the device pin. This register avoids the need for a read-modify-write sequence for unchanged bits.

• MASK_DATA_MSW:

  This register is the same as MASK_DATA_LSW, except it controls the upper 16 channels of the bank.

I/O Buffer Control

Software configures each GPIO as either an input, output, or interrupt input.

• DIRM control bit

  Direction mode controls whether the I/O pin is acting as an input or an output. This must be set to input to detect an interrupt and be routed to the DATA_RO register.

  • 0: enable I/O as an input for the interrupt detector and data register
  • 1: enable I/O as an output from the status/mask registers
• OEN control bit

  When the I/O is configured as an output, the OEN controls whether the output is enabled (OEN = 1) or in tristate mode (OEN = 1).

  Note: There are overriding tristate control registers in the PMC_IOP_SLCR and LPD_IOP_SLCR register sets. If a bit in the MIO_MST_TRIn register is set = 1, the output buffer is put in a tristate mode regardless of the state of the OEN signal state from the GPIO controller.

Interrupt Control

There are several interrupt control registers.

• INT_MASK masks the latched INT_STAT value. To generate an interrupt:
  • INT_MASK must = 0 (enable interrupt)
  • INT_STAT must = 1 (active interrupt)
• INT_EN is write-only. Write 1 to enable the interrupt; sets the INT_MASK bit = 0.
• INT_DIS is write-only. Write 1 to disable the interrupt; set the INT_MASK bit = 1.
• INT_STAT indicates if an interrupt event occurred, latched before INT_MASK.
• INT_TYPE is programmed by software to set level (0) or edge (1) sensitivity.
• INT_POLARITY selects between active-Low/falling (0) and active-High/rising (1) sensitivity.
• INT_ANY selects single edge sensitivity defined by INT_POLARITY (0) or either edge event (1).