GTY and GTYP Pipe Transceivers

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

Sixteen high-speed pipe transceivers are grouped into four quad banks. The transceiver pins can connect to several interfaces.

  • PCIe┬« controller 0 in the CPM
  • PCIe controller 1 in the CPM
  • High-speed debug port (HSDP), single channel
  • PL fabric interface (this path is available only for GTY XPipe transceivers used with CPM4)

Connections to the transceivers are illustrated in the Debug Host Interfaces section of the Integrated Debug chapter.

CPM Documentation

The details of the CPM implementation are available in these documents:

  • Versal ACAP CPM Mode for PCI Express Product Guide (PG346)
  • Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347) (includes pipe transceiver signal assignments)