Sixteen high-speed pipe transceivers are grouped into four quad banks. The transceiver pins can connect to several interfaces.
- PCIe® controller 0 in the CPM
- PCIe controller 1 in the CPM
- High-speed debug port (HSDP), single channel
- PL fabric interface (this path is available only for GTY XPipe transceivers used with CPM4)
Connections to the transceivers are illustrated in the DPC Interfaces section of the Debug Packet Controller chapter.