Glitch Filter

Versal ACAP Technical Reference Manual (AM011)

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1.5 English

The digital glitch filter is applied to the SDA and SCL inputs. This filter removes transients that occur on the inputs so the controller see the intended input signal level.

The filter logic is clocked by the APB programming interface clock (xxx_LSBUS_CLK). This clock is normally 100 MHz (10 ns).

In this case, the glitch filter is set to 50 ns by the reset default value. The length of filtering time is set by the I2C.GLITCH_CTRL [GF] bit field.

If the glitch filter control is set to 0, then the glitch filter is disabled.