HBM Interface

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The high-bandwidth memory (HBM) interface provides a highly parallel data interface to DRAM memory. The HBM interface is a convergence of fast memory, adaptable compute, and secure connectivity in a single platform. The series is designed to keep up with the higher memory needs of the most compute intensive, memory-bound applications

Versal HBM series devices, built on SSI technology, include high-bandwidth memory (HBM) DRAM integrated on the same silicon interposer as the SLRs. One or two, 4-high or 8-high stacks of memory are available, delivering a maximum capacity of 32 GB. The HBM interfaces with the SLRs through the silicon interposer with 16 channels of 64 bidirectional data signals per memory stack.

For memory-bound, compute-intensive applications, the series features heterogeneous integration of 3D IC memory, secure connectivity, and adaptive compute to eliminate performance bottlenecks.

For more information about the interface, see the High-Bandwidth Memory Interface section.