Hardware Interrupts

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The controller supports several types of interrupts.

Shared peripheral interrupt
Shared peripheral interrupts (SPIs) are peripheral interrupts that can be routed to a specific processor core that can handle the interrupt or a core that is configured to receive this type of interrupt. These interrupts can be group 0 or group 1, and can be either wire-based or message-based.
Private peripheral interrupt
Private peripheral interrupts (PPIs) target a single specific processor core and are independent for each core in the APU cluster. These interrupts are used when the peripherals are tightly coupled to a particular core, can be group 0 or group 1, and are only wire-based. All PPI interrupts are level sensitive.
  • PPI#22 – DCC interrupt
  • PPI#23 – PMU interrupt (performance monitor unit)
  • PPI#24 – CTI interrupt
  • PPI#25 – Virtual maintenance interface
  • PPI#26 – Hypervisor timer
  • PPI#27 – Virtual timer
  • PPI#28 – Legacy PL FIQ
  • PPI#29 – Secure physical timer interrupt
  • PPI#30 – Non-secure physical timer interrupt
  • PPI#31 – Legacy PL IRQ
Software generated interrupts
Software generated interrupts (SGIs) are inter-processor interrupts. SGIs can be generated by writing to the software generated interrupt register ( GICD_SGIR ). There are 16 SGIs available for each processor in the MPCore. These interrupts have no effect on the hardware.
Locality-specific peripheral interrupts for virtualization
Locality-specific peripheral interrupts (LPIs) are targeted peripheral interrupts that are routed to a specific processor in the MPCore. LPIs can only be non-secure group 1 interrupts and only with edge-triggered behavior. These interrupts are generated by a peripheral writing to a memory-mapped register in the GIC-500 interrupt controller and, consequently, are only message-based interrupts. The GIC-500 supports up to 56k LPIs. The cache size for frequently occurring MSI/MSI-x is 64 entries. The device ID is delivered to the GIC via the AWUSER bits.