The high-bandwidth memory (HBM) interface is a device option included in the AMD stacked silicon interconnect (SSI) technology devices. The HBM DRAM memory die are from third-party vendors and are integrated into the AMD device using a silicon interposer for connections to the HBM interfaces on the AMD die. The memory stacks can be one, two, four, or eight dies high plus a base DRAM controller die.
The HBM memory stacks can be 8 or 16 GB each and an integrated AXI HBM controller for each memory channel (8) in the stack. Each controller is divided into two semi-independent 64-bit pseudo channels that address a dedicated portion of the HBM. The controller and PHY operate at up to 1600 MHz for a transfer rate of 3200 MT/s. With 128 bits per channel, 8 channels per stack, and 2 stacks in most devices, this yields a maximum throughput of 819 GB/s.
The HBM interface is a device option. The devices with the HBM interface are listed in the Versal Architecture and Product Data Sheet: Overview (DS950).
Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313) describes the HBM interface. For the electrical characteristics, see Versal HBM Series Data Sheet: DC and AC Switching Characteristics (DS960).
Memory Access Restriction
Memory accesses to the HBM interface are normally aligned to a 16-byte address and a length that is a multiple of 16 bytes.
Accesses that are less than 16 bytes (or are not aligned to a 16-byte address) must be done with non-modifiable transaction requests (AxCACHE[1] parameter set to 0). Non-modifiable means the interconnect cannot break up the transaction into multiple transactions and it cannot combine the transaction with other memory transactions.
Physical Diagram
See the SSI High-Bandwidth Memory Package Concept section for a physical device diagram.