The high-bandwidth memory (HBM) interfaces are a device option included in some of the Xilinx stacked silicon interconnect (SSI) technology devices. The HBM DRAM memory die are from third-party vendors and are integrated into the Xilinx device using a silicon interposer for connections to the HBM interfaces on the Xilinx die. The memory stacks can be one, two, four, or eight dies high plus a base DRAM controller die.
Memory Access Restriction
Memory accesses to the HBM interface are normally aligned to a 16-byte address and a length that is a multiple of 16 bytes.
Accesses that are less than 16 bytes (or are not aligned to a 16-byte address) must be done with non-modifiable transaction requests (AxCACHE parameter set to 0). Non-modifiable means the interconnect cannot break up the transaction into multiple transactions and it cannot combine the transaction with other memory transactions.