High-level Address Map

Versal ACAP Technical Reference Manual (AM011)

Document ID

AM011

Release Date

2022-12-16

Revision

1.5 English

The high-level address map includes groups of register modules and memory spaces for the entire device.

Table 1. High-Level Address Map, 16 TB
Destination	Address Range		Size (KB)	Description
Destination	Start	End	Size (KB)	Description
DDRMC0_region0_mem	0x0000_0000	0x7FFF_FFFF	2 GB	DRAM Memory Controller 0, Region 0 (lower 2GB)
LPD_AXI_PL_mmap	0x8000_0000	0x9FFF_FFFF	512 MB	PS-to-PL AXI Interface from LPD
FPD_AXI_PL_mmap	0xA400_0000	0xAFFF_FFFF	192 MB	PS-to-PL AXI Interface from FPD, lower
FPD_AXI_PL_mmap	0xB000_0000	0xBFFF_FFFF	256 MB	PS-to-PL AXI Interface from FPD, upper
OSPI_mem	0xC000_0000	0xDFFF_FFFF	512 MB	Octal-SPI Linear Mode memory space
CPM4_PCIe0_mem	0xE000_0000	0xEFFF_FFFF	256 MB	PCIe Region 0 in CPM4
PMC_Peripherals	0xF100_0000	0xF8FF_FFFF	128 MB	PMC Peripheral Register Modules
GIC_Local_mmap	0xF900_0000	0xF90B_FFFF	768 KB	RPU and APU local generic interrupt controller (GIC) access
FPD_Peripherals	0xFD00_0000	0xFDFF_FFFF	16 MB	FPD Peripheral Register Modules
LPD_Peripherals_Memory	0xFE00_0000	0xFFAF_FFFF	~11 MB	LPD Memory and Peripheral Register Modules
PSM_Peripherals_Memory	0xFFC0_0000	0xFFCF_FFFF	1 MB	PSM Memories and Register Modules
OCM_Memory	0xFFFC_0000	0xFFFF_FFFF	256 KB	On-chip Memory space
RPU_TCM_Caches	0xFFE0_0000	0xFFED_7FFF	864 KB	RPU TCM and Cache Memory Access Locations
CPM5_Peripherals_Memory	0xE000_0000	0xFCFF_FFFF	~464 MB	CPM5 Peripheral Register Modules and Memory
Four PMC alias regions	0x001_0000_0000	0x001_1FFF_FFFF	512 MB	Four alias regions provide windows into base PMC and SSIT-based PMCs. Note: All four alias regions provide a window into associated local PMC address space 0xF000_0000 to 0xF7FF_FFFF (128 MB).
FPD_AXI_PL_high	0x004_0000_0000	0x005_FFFF_FFFF	8 GB	PS FPD-to_PL AXI Interface, High Region (aka PS_TO_PL_0)
PCIe0_region1	0x006_0000_0000	0x007_FFFF_FFFF	8 GB	PCIe Region 1
DDRMC0_region1_mem	0x008_0000_0000	0x00F_FFFF_FFFF	32 GB	DDR Memory Controller 0, Region 1
HBM_memory	0x040_0000_0000	0x07F_FFFF_FFFF	256 GB	HBM Controllers 0 to 3
PCIe_region_2	0x080_0000_0000	0x0BF_FFFF_FFFF	256 GB	PCIe Region 2
DDRMC0_regions_2_3_mem	0x0C0_0000_0000	0x1B7_7FFF_FFFF	990 GB	DDR Memory Controller 0, Regions 2 and 3
AI_Engine	0x200_0000_0000	0x200_FFFF_FFFF	4 GB	AI Engine Programming and Interface Tiles
PL_mmap	0x201_0000_0000	0x4FF_FFFF_FFFF	~4 TB	PL Memory Space
PS_PL_mmap	0x400_0000_0000	0x4FF_FFFF_FFFF	1 TB	PS to PL Memory Space
DDRMC_1_3_regions_0_1_mem	0x500_0000_0000	0x7FF_FFFF_FFFF	3 TB	DDR Memory Controllers 1 to 3 (regions 0 and 1 for each controller)