The clock control and status bits are listed in the following table.
SD_EMMC Register | Field Name, Bits | Setting | Description |
---|---|---|---|
Clock Controls | |||
CLK_CTRL |
[SDClkFreqDiv_U, 7:6] |
Note 1 | Clock frequency divider |
[IntClkEn, 0] | 1 | TX output enable | |
[SDClkEn, 2] | 0 | Clock enable | |
Clock Status | |||
CLK_CTRL | [IntClkStable, 1] | 1 |
Read-only: |
DLL Clock Controls | |||
OTAP_DLY | [sel, 5:0] | Note 2 | Output tap delay select |
ITAP_DLY | [sel, 7:0] | Note 2 | Input tap delay select |
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