High-speed Clock Control Settings

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The clock control and status bits are listed in the following table.

Table 1. High-speed Clock Control Settings
SD_EMMC Register Field Name, Bits Setting Description
Clock Controls
CLK_CTRL

[SDClkFreqDiv_U, 7:6]
[SDClkFreqDiv_L, 15:8]

Note 1 Clock frequency divider
[IntClkEn, 0] 1 TX output enable
[SDClkEn, 2] 0 Clock enable
Clock Status
CLK_CTRL [IntClkStable, 1] 1

Read-only:
0: Not ready
1: Ready

DLL Clock Controls
OTAP_DLY [sel, 5:0] Note 2 Output tap delay select
ITAP_DLY [sel, 7:0] Note 2 Input tap delay select
  1. Set these bits based on the required frequency of the SDx_REF_CLK and SDx_CLK. See Clock Frequency Divider Register Settings. For frequencies above 25 MHz, the SDx_REF_CLK is set to 200 MHz.
  2. These values are used to manually tune the DLL clock phases RX. See DLL Programming Model.