The I/O buffer pin banks are listed in the following table.
| Bank Name | Pin Count | Buffer Type | Description |
|---|---|---|---|
| PMC DIO Bank | 15 | Digital | Dedicated I/O with POR_B, REF_CLK, JTAG, and boot mode. |
| PMC DIO_A Bank | 4 | Analog | |
|
PMC MIO Bank 0 |
52 | Digital |
Multiplexed I/O for boot devices and peripherals in the PMC and LPD IOPs. See Multiplexed I/O Signals and Pins and Output Buffer Control Registers. |
| LPD MIO Bank | 26 | Digital | |
| PL XPIO | 54 per bank | XP IOB | The XPIO banks are normally used by the DDRMC, but are available for use by the PL fabric except for the XPIO banks located in the corners of the die. The XP I/O interconnect logic (IOL) and I/O block (IOB) resources are described in the Versal ACAP SelectIO Resources Architecture Manual (AM010) with the layout described in Versal ACAP Packaging and Pinouts Architecture Manual (AM013). |
| PL HDIO | Varies | Digital | Multiple banks of HDIO buffers connect PL to device pins. The HDIO IOL and IOB resources are described in the Versal ACAP SelectIO Resources Architecture Manual (AM010). |
| GTYP 1 | 16 | Transceiver |
CPipe GTYP transceivers connect CPM5 PCIe lanes and Aurora debug to I/O pins. PL fabric GTYP transceivers connect the PL to I/O pins. |
| GTY 1 | Varies | Transceiver | XPipe GTY transceivers connect CPM4 PCIe lanes, Aurora debug, and PL fabric to I/O pins. PL fabric GTY transceivers connect the PL to I/O pins. |
| GTM | Varies | Transceiver | Listed in the Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957). |
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