The programming sequence is as follows using the CLK_CTRL register.
- Disable the clock by clearing [IntClkEn, 0] to 0 and [SDClkEn, 2] to 0.
- Set the clock divisor value using [SDClkFreqDiv_U] and [SDClkFreqDiv_L] and
set the [IntClkEn, 0] bit to a 1.Note: The internal clock enable register value [IntClkEn, 0] needs to be cleared to 0 for at least one SD_CLK cycle whenever the clock frequency is changed. This can be timed using the CPU clock or timer.
- Read the [IntClkStable, 1] bit until it reads a 1, which means the internal clock is stabilized.
- Enable the SD clock by setting [SDClkEn, 2] to 1.