I/O coherency (one-way) enables processors and DMA units to snoop the APU L2 cache. If there is a read hit in the L2 cache, then the L2 cache sources the data. If there is a write hit in the L2 cache, then the action depends on the coherency policy requested by the transaction host. I/O coherency with the CCI is supported by the PL_ACELITE_FPD interface attached to an ACE-Lite port of the CCI. The source can also access the SMMU and CCI via the NoC.
The ACE coherency protocol ensures that all processors and DMA units observe the correct data value at any given address location by enforcing that only one copy exists whenever a store occurs to the location. After each store to a location, other processors and DMA units can obtain a new copy of the data for their own local cache, allowing multiple copies to exist. See the Arm® AMBA® AXI and ACE protocol specification for a detailed overview.