I/O Interface Control Registers

Versal ACAP Technical Reference Manual (AM011)

Document ID

AM011

Release Date

2022-12-16

Revision

1.5 English

The I/O interface controls are located in the SD_EMMC and PMC_IOP_SLCR register modules. The majority of these registers are for configuring the SDx_CLK output to the flash memory device.

Note: The system reference clocks that drive the DIV_CLK and DLL modules are listed in the table in the System-Related Registers section.

SD_eMMC Register Module

The following I/O interface control registers are included in the SD_EMMC register module.

Note: These registers are defined with 16-bit data widths. However, all registers are accessed as 32-bit read/write transfers with addresses aligned on a 32-bit boundary.

Table 1. SD_eMMC I/O Interface Control Registers in the SD_eMMC Register Module
Register Name	Width	Address Offset	Access Type	Description
SD_CLK Control and Status
CLK_CTRL	16	`0x02C`	Mixed	Clock frequency control and state
Read Preset Values
PRE_VAL_0 PRE_VAL_1 PRE_VAL_2	16	`0x060` `0x062` `0x064`	R	Read the preset values for SD_CLK frequency, clock generator, and driver strength select value.

PMC_IOP_SLCR Register Module

The I/O clocks are sourced from either the DIV_CLK or DLL clock modules.

SD_eMMC are further configured by several registers in the PMC_IOP_SLCR register set. All registers listed in the following table are defined as 32 bits.

Table 2. SD_eMMC I/O Interface Control Registers in the PMC IOP SLCR Register Module
Register Name		Access Type	Description
SD_eMMC Controller 0	SD_eMMC Controller 1	Access Type	Description
Clock and Control
SD0_Clk_Ctrl	SD1_Clk_Ctrl	RW	SD feedback clock routing
SD0_Ctrl	SD1_Ctrl	RW	Controller mode: SD or eMMC
SD0_Cfg_Reg1 SD0_Cfg_Reg2 SD0_Cfg_Reg3	SD1_Cfg_Reg1 SD1_Cfg_Reg2 SD1_Cfg_Reg3	RW	Configuration registers
Presets
SD0_Init_Preset SD0_DSP_Preset SD0_HSPD_Preset SD0_SDR12_Preset SD0_SDR25_Preset SD0_SDR50_Preset SD0_SDR104_Preset SD0_DDR50_Preset	SD1_Init_Preset SD1_DSP_Preset SD1_HSPD_Preset SD1_SDR12_Preset SD1_SDR25_Preset SD1_SDR50_Preset SD1_SDR104_Preset SD1_DDR50_Preset	RW	Initialization for SD: Init preset Default speed High speed SDR12 SDR25 SDR50 SDR104 DDR50
Miscellaneous Registers
SD0_DLL_Ctrl	SD1_DLL_Ctrl	Mixed	SD DLL status
SD0_Rx_Tuning_Sel	SD1_Rx_Tuning_Sel	R	DLL RX clocking
SD0_DLL_DivMap	SD1_DLL_DivMap	RW	DLL divider mapping
SD0_CD_Ctrl	SD1_CD_Ctrl	RW	SD card detect
SD0_MaxCurr_1p8 SD0_MaxCurr_3p0 SD0_MaxCurr_3p3	SD1_MaxCurr_1p8 SD1_MaxCurr_3p0 SD1_MaxCurr_3p3	RW	Maximum current: 1.8, 3.0, and 3.3V