The I/O interface controls are located in the SD_EMMC and PMC_IOP_SLCR register modules. The majority of these registers are for configuring the SDx_CLK output to the flash memory device.
SD_eMMC Register Module
The following I/O interface control registers are included in the SD_EMMC register module.
|Register Name||Width||Address Offset||Access Type||Description|
|SD_CLK Control and Status|
||Mixed||Clock frequency control and state|
|Read Preset Values|
Read the preset values for SD_CLK frequency, clock generator, and driver strength select value.
PMC_IOP_SLCR Register Module
The I/O clocks are sourced from either the DIV_CLK or DLL clock modules.
SD_eMMC are further configured by several registers in the PMC_IOP_SLCR register set. All registers listed in the following table are defined as 32 bits.
|Register Name||Access Type||Description|
|SD_eMMC Controller 0||SD_eMMC Controller 1|
|Clock and Control|
|SD0_Clk_Ctrl||SD1_Clk_Ctrl||RW||SD feedback clock routing|
|SD0_Ctrl||SD1_Ctrl||RW||Controller mode: SD or eMMC|
Initialization for SD:
|SD0_DLL_Ctrl||SD1_DLL_Ctrl||Mixed||SD DLL status|
|SD0_Rx_Tuning_Sel||SD1_Rx_Tuning_Sel||R||DLL RX clocking|
|SD1_DLL_DivMap||RW||DLL divider mapping|
|SD0_CD_Ctrl||SD1_CD_Ctrl||RW||SD card detect|
|RW||Maximum current: 1.8, 3.0, and 3.3V|