I2C Registers

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

Each controller has a set of I2C registers. The PMC has a separate register set, PMC_I2C from the LPD controllers, LPD_I2C. The controllers have identical functionality with separate memory-mapped register base address locations:

  • PMC_I2C base address is 0xF100_0000
  • LPD_I2C0 base address is 0xFF02_0000
  • LPD_I2C1 base address is 0xFF03_0000

The registers are listed in the following table.

Table 1. I2C Register Overview
Register Name Address Offset Access Type Description

PMC_I2C.Control
LPD_I2C.Control

0x000 R/W I/O protocol, clock divider

PMC_I2C.Status
LPD_I2C.Status

0x004   Read data available

PMC_I2C.Address
PMC_I2C.Data
LPD_I2C.Address
LPD_I2C.Data

0x008

0x00C

R/W

Address; 7 or 10-bit field
8-bit data field

PMC_I2C.Transfer_Size
LPD_I2C.Transfer_Size

0x014 R/W 0 to 255 transfer size

PMC_I2C.Slave_mon_pause
LPD_I2C.Slave_mon_pause

0x018 R/W 0 to 7 pause interval

PMC_I2C.Timeout
LPD_I2C.Timeout

0x01C R/W 32 to 127 timeout interval

PMC_I2C.ISR
PMC_I2C.IMR
PMC_I2C.IER
PMC_I2C.IDR
LPD_I2C.ISR
LPD_I2C.IMR
LPD_I2C.IER
LPD_I2C.IDR

0x010
0x020
0x024
0x028

R, W1C
R
W
W

Interrupts: status is after mask. Enabled interrupts are OR'ed together and generate a system interrupt.

PMC_I2C.Glitch_Filter
LPD_I2C.Glitch_Filter

0x02C R/W

Glitch filter control

PMC_I2C.Data_Hold_Ctrl
LPD_I2C.Data_Hold_Ctrl

0x030 R/W

Data hold control