IP Block Versions

Versal ACAP Technical Reference Manual (AM011)

Document ID
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1.5 English

The following table lists the PMC-PS implementation summary organized by TRM section.

Table 1. PMC-PS Implementation Summary Organized by TRM Section
Functional Unit Description Instances, Description, and IP Version
Engines section
APU MPCore Application processor cores. Dual Arm Cortex-A72 processors with v8-A architecture and NEON and VFPv4 floating point A74-MP and MP054 (Arm version r0p3-00rel0).

Cryptography extension (A72-Crypto, MP055) ( versionr0p2-00rel0).

APU GIC Application processor generic interrupt controller.

Generic interrupt controller, GIC-500
(Arm version r1p1-00rel0).

RPU MPCore Real-time processor cores. Dual processor cores, Cortex-R5F (Arm version AT570-r1p3-00rel0).
RPU GIC Real-time processor generic interrupt controller.

(Arm version r0p0-00rel2).

LPD_DMA Descriptor-driven, general purpose DMA unit. LPD DMA Controller chapter.
Embedded Processor, Configuration, and Security Units section
AES-GCM Security engine for encryption and decryption.  

Symmetric key cryptography for encryption and decryption, AES.
(Athena version ro-2017-12-12).

BBRAM controller

Battery-backed RAM controller
Battery-Backed RAM.


Configuration frame unit receives commands and read/writes PL configuration regions
Configuration Frame Unit.


DMA0 and DMA1; streaming and memory-to-memory transactions on PMC interconnect port.


Debug packet controller; connected to the PMC main switch, JTAG, Aurora HSDP, and PL
Debug Packet Controller.

eFUSE controller

Controller for eFUSE array.

eFUSE cache

Cache of the eFUSEs.

JTAG TAP controller

TAG test access port controller for boundary scan and Xilinx opcodes.

JTAG Arm DAP controller

Debug access port controller for PS
Arm DAP Controller.

PPU Platform Processing Unit



Security public-key cryptography engine for authentication (RSA/ECDSA)


Public-key crypto system, RSA,  and elliptic curve digital signature algorithm,ECDSA, public-key cryptography enables authentication.
(IP Cores version 5X-409603203 r2.0_12_20_2016).

PMC_RTC Real-Time Clock battery backup time keeping.  

Boot interface works with SelectMAP and JTAG data flows, SBI for JTAG and SelectMAP.

PMC_SHA3 Security engine for secure hash to authenticate. SHA3-384

True random number generator
True Random Number Generator.

True random number generator, TRNG,
(IP Cores version MP32 core r1.5).


System  monitor for measuring temperature and voltage
(root and satellite SYSMON units).

Main SYSMON is in the PMC, others are in FPD and elsewhere.
Interconnect section
AXI interconnect  

AXI interconnect switches, NIC-400.
AXI Interconnect Switches
(Arm version r0p2).

FPD SMMU System memory management unit, SMMU-500, supports memory virtualization and access protection of peripherals and memory System Memory Management Unit.

Includes 7 TBU instances.
(Arm TCU version is r2p4,
TBU version is r2p1).

APU cache coherency  

Cache coherent interconnect, CCI-500
Cache Coherent Interconnect
(Arm version PL422-r1p0-00rel0).

Xilinx memory protection unit (XMPU) Xilinx Memory Protection Unit.


Xilinx peripheral protection unit (XPPU) Xilinx Peripheral Protection Unit. PMC_XPPU, PMC_XPPU_NPI
Timers, Counters, and RTC section.

System counter, SCNTR.
System Timestamp Counter chapter
(Arm version 1.0).


System watchdog timer, SWDT, helps to maintain a healthy and secure system by detecting errant software, deadlock conditions, tampering, and unexpected behavior System Watchdog Timers.

System watchdog timer, SWDT
(Xilinx version 0.08). LPD_SWDT

TTC Triple timer counter, TTC Triple-Timer Counters Triple timer counter, TTC. Four in PS LPD. (Cadence version T-CS-PE-0005-100).
I/O Peripheral Controllers section
CAN FD controller Controller area network with flexible data-rage, CAN FD.

Controller area network with flexible data-rate, CAN FD (Xilinx version v3.0).

GEM controller  

Gigabit Ethernet MAC controller, GXL and RGMII
Gigabit Ethernet MAC chapter
(Cadence version r1p12).
Two in PS LPD.

GPIO General purpose I/O with output, tristate, and input. Input can be read and generate a system interrupt GPIO Controller.

PMC_GPIO has two MIO banks (52 channels total) and two EMIO banks (64 channels total).
PS LPD_GPIO has one MIO bank (26 channels) and one EMIO bank (32 channels).


I2C controller
I2C Controller
(Cadence, dcw0701_R114_f0100_final).

Inter-integrated circuit (I2C) controller.
Two LPD_I2Cx.
One PMC_I2C.
One SysMon_I2C.

I3C I3C controller.  
SPI controller  

SPI controller (two in LPD)
SPI Controller chapter.
(Cadence version r112).

UART SBSA controller

UART SBSA controller, see UART Controller chapter.
(Arm version r1p5-00rel1).

UART SBSA controller:
two in PS LPD.

USB 2.0 controller  

USB 2.0 controller
USB 2.0 Controller chapter.
(Synopsys version USB3 3.30a core configured for USB 2.0).

USB 3.0 controller    
Flash Memory Controllers section

Octal SPI flash memory controller, see the Octal SPI Controller chapter
(Cadence version DNV3100_R003_F004).

OSPI flash memory controller.

Quad SPI flash memory controller, see the Quad SPI Controller chapter
(same as MPSoC with DMA addition).

QSPI flash memory controller.

SD/SDIO/eMMC controller (eMMC v4.51), SD v4.51 Controller

SD_eMMC flash memory controller
(Arasan version 1p48_140929).

Clocks, Resets, and Power section
PMC IRO CLK Silicon-based internal ring oscillator, trimmed.

PMC Source Clocks.

PLLs PLL clock controllers PLL Clock Generators.


PMC ClkMon

Clock monitor
Clock Monitor.

Test and Debug section
Integrated debug High-speed debug port, HSDP, provides a pathway to the GTY and GTYP transceivers for the Aurora packet-based debug unit.  
Debug packet controller See Debug Packet Controller  
CoreSight CoreSightâ„¢ debug.

CoreSight debug, CS_SoC-400, TM100).
(Arm, r3p2-00rel1).

CoreSight embedded logic analyzer. CoreSight embedded logic analyzer, ELA-500, TM300. (Arm, r2p2-00rel0).
CoreSight logic analyzer kit. CoreSight logic analyzer kit LAK-500 A/I. (Arm, r1p0-00rel0).
CoreSight Stream. CoreSight Stream (STM-500, TM963) (Arm, r0p1-00rel1).