Implementation Table Links

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2023-10-05
Revision
1.6 English

The processing system and platform management functional units are summarized in implementation tables that are included in various chapters of the TRM. These tables are generally located near the beginning of a chapter. They list the implementation of the processor, controller, interface, peripheral, RAM, and other functional units for each device generation.

The SoC generations include:

  • AMD UltraScale+™ MPSoCs
  • Versal devices

The functional units are listed in the following sections:

The lists, comparisons, and revisions are captured in several topics throughout the TRM as referenced in this section.

Platform Boot, Control, and Status Implementations (Section III)

Embedded Processor, Configuration, and Security Implementations (Section VII)

Interconnect Implementations (Section VIII)

Interconnect includes AXI switches, system memory management unit (SMMU), APU cache coherent interconnect, memory protection units (XPPU, XMPU), and system watchdog timer (SWDT) units.

System Interrupts and Errors Implementations (Section IX)

Timers, Counters, and RTC Implementations (Section X)

Memory Controllers, Integrated RAMs, and Storage Registers Implementations (Section XI)

Clocks, Resets, and Power Implementations (Section XIV)

NoC, DDR, and other Integrated Hardware

The functionality of the NoC interconnect, DDR memory, PL, and the integrated hardware is described in other documents. The instances of the integrated hardware for a particular device are listed in the Versal Architecture and Product Data Sheet: Overview (DS950).